Background
- Time: May 2025
- Context: Main practical assignment for the course “Computer Organization”.
GitHub Repository
Highlights
- Implemented a five-stage pipelined CPU based on the RISC-V 32I instruction set on the EGO1 FPGA board.
- Added UART communication and branch prediction support.
- Built a Python GUI frontend for real-time visualization of registers and pipeline states.
Tech Stack
- Verilog
- RISC-V 32I
- FPGA (EGO1)
- UART
- Python GUI
Comment
This is one of my favorite project. Our team spend nearly 100 hours for this course project! Not because of requirements but just feeling interesting to make the theory we learned from class and textbook come true. Every night we gather in a lab room after class and work until 1-3 am, feeling fulfilled and calm. We got 118.5 out of 100 (theoretical maximum score) for this project, thanks for my teammates and my teachers.
